Discrete cosine transformation operation circuit

ABSTRACT

One multiplier  13  operated at a normalized frequency  4  is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder  15  to determine cumulative addition results corresponding to the sum (x 0 +x 7 ) and the difference (x 0 −x 7 ) of a pair of elements (x 0,  x 7 ) of data to be outputted from a one-dimensional DCT operation circuit  1.  The paired cumulative addition results are added and subtracted by an adder  17  and a subtracter  18,  respectively, to determine the elements (x 0,  x 7 ). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.

TECHNICAL FIELD

The present invention relates to a technique for processing image dataand a technique for decompressing the compressed image data and, moreparticularly, to a technique which is useful when applied to a discretecosine transformation operation circuit in the JPEG (Joint PhotographicExperts Group) system or the MPEG (Motion Picture Experts Group) system.

BACKGROUND ART

In the prior art, the discrete cosine transformation (DCT) operationcircuit is equipped with a plurality of multipliers for multiplyinginput data and DCT transformation coefficients.

In the case of a DCT matrix operation composed of 8 rows and 8 columns(8×8), as generally used in the JPEG system or the MPEG system, forexample, there are provided eight multipliers.

However, the multiplier is equipped with a number of gates to raise adrawback that the gate scale of the entire operation circuit isenlarged. In addition, the operating frequency of the multipliers isequal to the frequency (which is equal to the frequency of the inputtingtiming of the input data) of the outputting timing of the DCT operationresult, and the product of their ratio (i.e., “1”) and the number ofmultipliers is as large as “8” to raise another drawback that the powerconsumption is increased. Specifically, the multipliers are driven witha high operating frequency, so that they consume a high power whendriven. The number of the multipliers is as large as eight in the priorart so that the power consumption is further increased.

As a measure for improvement, there is disclosed in Japanese PatentLaid-Open No. 4-280368, a DCT operation circuit which is constructed byusing two multipliers operated with a frequency four times as high asthat of the inputting timing of the data inputted to the DCT operationcircuit. In this DCT operation circuit, for example, an input data x₁₁is multiplied by DCT transformation coefficients d₁₁, d₂₁, d₃₁ and d₄₁by one multiplier, and by DCT transformation coefficients d₅₁, d₆₁, d₇₁and d₈₁ by the other multiplier, thereby obtaining four multiplicationresults x₁₁d₁₁, x₁₁d₂₁, x₁₁d₃₁ and x₁₁d₄₁, and four multiplicationresults x₁₁d₅₁, x₁₁d₆₁, x₁₁d₇₁ and x₁₁d₈₁. The eight multiplicationresults thus obtained are stored in eight registers.

Another input data x₂₁ is also multiplied by DCT transformationcoefficients d₁₂, d₂₂, d₃₂ and d₄₂ by one multiplier and by DCTtransformation coefficients d₅₂, d₆₂, d₇₂ and d₈₂ by the othermultiplier, thereby obtaining four multiplication results x₂₁d₂₂,x₂₁d₂₂, x₂₁d₃₂ and x₂₁d₄₂, and four multiplication results x₂₁d₅₂,x₂₁d₆₂, x₂₁d₇₂ and x₂₁d₈₂. The eight multiplication results thusobtained are stored in eight registers. Moreover, the eightmultiplication results x₂₁d₁₂, x₂₁d₂₂, x₂₁d₃₂, x₂₁d₄₂, x₂₁d₅₂, x₂₁d₆₂,x₂₁d₇₂ and x₂₁d₈₂ and the preceding eight multiplication results x₁₁d₁₁,x₁₁d₂₁, x₁₁d₃₁, x₁₁d₄₁, x₁₁d₅₁, x₁₁d₆₁, x₁₁d₇₁ and x₁₁d₈₁ read out fromthe foregoing eight registers are added by adders, and the additionresults are stored again in the aforementioned eight registers.

By repeating the operation composed of such multiplication andcumulative addition eight times, the elements y₁₁ to y₈₁ of the matrixare determined. By repeating the operation eight times, moreover, allthe elements of the matrix are determined. Thus, the one-dimensional 8×8DCT matrix operation is ended.

In the DCT operation circuit disclosed in Japanese Patent Laid-Open No.4-280368, however, two multipliers are used and therefor improvement inthe circuit scale is still needed. In other words, the number ofmultipliers is desirably reduced to one so that the circuit scale may beminimized.

In the DCT operation circuit of the aforementioned Laid-Open, moreover,the multipliers are operated with a frequency four times as high as thatof the inputting timing of the data inputted to the DCT operationcircuit. As a result, the product of the ratio (hereinafter referred toas the “normalized frequency”) of the operating frequency of themultipliers to the frequency of the inputting timing of the data and thenumber of multipliers is “8”, and no improvement has been made in thepower consumption. In order to reduce the power consumption, the productof the normalized frequency and the number of multipliers is desired tobe minimized as much as possible.

The invention has been made in view of the circumstances and has a mainobject to provide a discrete cosine transformation operation circuitwhose power consumption is reduced by setting the product of the numberof multipliers of a one-dimensional discrete cosine transformationoperation circuit and the normalized frequency at 4 and to reduce thecircuit scale by setting the number of multiplier at 1.

The foregoing and other objects and novel features of the invention willbecome apparent from the following description to be made with referenceto the accompanying drawings.

DISCLOSURE OF INVENTION

The summary of representatives of the aspects of the invention to bedisclosed herein will be described in the following.

In the discrete cosine transformation operation circuit of theinvention, more specifically, there is provided one multiplier which isoperated with a frequency four times as high as that of the inputtingtiming of the data to be inputted to the discrete cosine transformationoperation circuit to sequentially multiply the elements of the DCTtransformation coefficients and the elements of the input datarespectively. The multiplication results are added by the cumulativeadder to determine a pair of cumulative addition results whichcorrespond to the sums and differences of the paired elements of thedata to be outputted from the discrete transformation operation circuit.The operations for determining the paired elements of the output data byadding and subtracting the cumulative addition results by the adder andthe subtracter specific times the number of which is one-half of thenumber of elements of the column of the matrix of the input data. Allthe elements of the matrix of the output data are determined byperforming those operations specific times the number of which is equalto the number of elements of the row of the matrix of the input data.

In the discrete cosine transformation operation circuit of theinvention, more specifically, there is provided one multiplier which isoperated with a frequency four times as high as that of the inputtingtiming of the data to be inputted to the discrete cosine transformationoperation circuit to sequentially multiply the elements of the DCTtransformation coefficients by the elements of the input datarespectively. The multiplication results are added as they are by thefirst cumulative adder, and the signs are alternately inverted toperform addition by the second cumulative adder specific times thenumber of which is one-half of the number of elements of the row of thematrix of the input data, and thereby to determine the elements of thecolumn of the matrix of the output data. These operations are performedspecific times the number of which is equal to the number of elements ofthe column of the matrix of the input data to determine all the elementsof the matrix of the output data.

Moreover, there are provided two multipliers to be operated with afrequency two times as high as that of the inputting timing of the datato be inputted to the discrete cosine transformation operation circuit,the DCT transformation coefficients are divided into two sets and storedin a ROM so that the respective multiplications of the elements of thesets of the DCT transformation coefficients and the elements of theinput data may be simultaneously performed by the two multipliers.

One or both of the discrete cosine transformation operation circuits areused to construct a two-dimensional discrete cosine transformationoperation circuit comprising: a pair of one-dimensional discrete cosinetransformation operation circuits; and an inverted RAM for performingthe matrix operations, in which the elements of a row and the elementsof a column of a matrix composed of operation results x₀₀, x₀₁, x₀₂, . .. received from the one-dimensional DCT operation circuit on the inputside, are exchanged, to output the operation results x₀₀, x₁₀, x₂₀, . .. to the one-dimensional DCT operation circuit on the output side.

According to the above-specified means, the product of the number ofmultipliers and the normalized frequency is 4 in the one-dimensionaldiscrete cosine transformation operation circuit, so that the powerconsumption can be reduced. Thanks to the single multiplier, moreover,the scale of the discrete cosine transformation operation circuit isreduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a DCT operation circuit of a firstembodiment schematically;

FIG. 2 is a time chart showing a part of the operation timings of theDCT operation circuit;

FIG. 3 is a block diagram showing a DCT operation circuit of a secondembodiment schematically;

FIG. 4 is a time chart showing a part of the operation timings of theDCT operation circuit;

FIG. 5 is a block diagram showing a DCT operation circuit of a thirdembodiment schematically;

FIG. 6 is a time chart showing a part of the operation timings of theDCT operation circuit;

FIG. 7 is a block diagram showing a DCT operation circuit of a fourthembodiment schematically;

FIG. 8 is a time chart showing a part of the operation timings of theDCT operation circuit;

FIG. 9 is a block diagram showing a DCT operation circuit of a fifthembodiment schematically; and

FIG. 10 is a time chart showing a part of the operation timings of theDCT operation circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram showing a discrete cosine transformation (DCT)operation circuit of a first embodiment schematically. In this DCToperation circuit 1, input data are inputted through a shift register10, a hold register 11 and a multiplexer 12 to a multiplier 13, and DCTtransformation coefficients, read out of a coefficient storage ROM 14,are inputted to the multiplier 13, so that those input data and the DCTtransformation coefficients are multiplied.

The results of multiplication are added by a cumulative adder 15 and areoutputted through a demultiplexer 16 to an adder 17 and a subtracter 18,so that the output data, determined by the addition and subtraction, areoutputted through registers 19A, 19B and 20 and a multiplexer 21.

An address counter 23 is connected with the multiplexer 12 and thecoefficient storage ROM 14, the DCT transformation coefficientcorresponding to an address designated by incrementing the addresscounter 23 is outputted from the coefficient storage ROM 14, and thedata corresponding to the address are outputted from the hold register11 by the multiplexer 12.

The input/output timings of the data in the individual registers 10, 11,19A, 19B and 20, the multiplexers 12 and 21 and the cumulative adder 15and the increment timing of the address counter 23 are controlledaccording to timing signals generated from a timing control unit 22.Here, FIG. 1 is a table prepared by using a reference clock CLK(frequency: φ0) inputted to the timing control unit 22 and thefrequencies expressed using φ (φ is the frequency of the input timingsof data to the shift register 10) of the timing signals outputted fromthe timing control unit 22 to the shift register 10, the hold register11, the multiplexers 12 and 21, the cumulative adder 15, the registers19A, 19B and 20 and the address counter 23.

This DCT operation circuit 1 produces two DCT operation results, whenone column of data of an input matrix are inputted to the multiplier 13,by exploiting the regularity of the DCT transformation coefficients.

The regularity of the DCT transformation coefficients will be describedat first.

For example, one-dimensional inverse DCT operations of 8×8 are expressedby a product of a matrix of the DCT transformation coefficients and aninput coefficient matrix, as by Formula (1). $\begin{matrix}{\begin{pmatrix}{x0} \\{x1} \\{x2} \\{x3} \\{x4} \\{x5} \\{x6} \\{x7}\end{pmatrix} = {\begin{pmatrix}d & a & b & c & d & e & f & g \\d & c & f & {- g} & {- d} & {- a} & {- b} & {- e} \\d & e & {- f} & {- a} & {- d} & g & b & c \\d & g & {- b} & {- e} & d & c & {- f} & {- a} \\d & {- g} & {- b} & e & d & {- c} & {- f} & a \\d & {- e} & {- f} & a & {- d} & {- g} & b & {- c} \\d & {- c} & f & g & {- d} & a & {- b} & e \\d & {- a} & b & {- c} & d & {- e} & f & {- g}\end{pmatrix}\quad \begin{pmatrix}{X0} \\{X1} \\{X2} \\{X3} \\{X4} \\{X5} \\{X6} \\{X7}\end{pmatrix}}} & (1)\end{matrix}$

In this Formula, the 8×1 matrix on the lefthand side is theone-dimensional inverse DCT operation result, and the 8×8 matrix and the8×1 matrix on the righthand side are the DCT transformation coefficientsand the input data, respectively. Here, the coefficients a, b, c, d, e,f and g in the DCT transformation matrix are expressed as follows.

a=cos (π/16)/{square root over (2)}

b=cos (2π/16)/{square root over (2)}

c=cos (3π/16)/{square root over (2)}

d=cos (4π/16)/{square root over (2)}

e=cos (5π/16)/{square root over (2)}

f=cos (6π/16)/{square root over (2)}

g=cos (7π/16)/{square root over (2)}

Formula (1) can be transformed into Formula (2). The DCT operationcircuit 1 produces the one-dimensional inverse DCT operation results byusing the regularity of Formula (2). Here in Formula (1) and Formula(2), only the first column of the 8×8 matrix is expressed for the inputdata and the output data, but the second to eighth columns are similarto the first column. $\begin{matrix}{\begin{pmatrix}{{x0} + {x7}} \\{{x1} + {x6}} \\{{x2} + {x5}} \\{{x3} + {x4}} \\{{x0} - {x7}} \\{{x1} - {x6}} \\{{x3} - {x4}} \\{{x2} - {x5}}\end{pmatrix} = {2\quad \begin{pmatrix}\begin{matrix}b & f & d & d \\f & {- b} & d & {- d} \\{- f} & b & d & {- d} \\{- b} & {- f} & d & d\end{matrix} & 0 \\0 & \begin{matrix}a & c & e & g \\c & {- g} & {- a} & {- e} \\g & {- e} & c & {- a} \\e & {- a} & g & c\end{matrix}\end{pmatrix}\quad \begin{pmatrix}{X2} \\{X6} \\{X0} \\{X4} \\{X1} \\{X3} \\{X5} \\{X7}\end{pmatrix}}} & (2)\end{matrix}$

The DCT operation circuit 1 will be described in detail for the case ofFormula (2), for example, with reference to the timing chart shown inFIG. 2. Here, input timings X0′, X1′, X2′, X3′, X4′, X5′ and X6′ of theshift register 10 denote the data to be newly inputted to the shiftregister 10 while data X0, X1, X2, X3, X4, X5, X6 and X7 inputted at theimmediately preceding cycle to the shift register 10, are subjected tothe DCT transformation (this holds for FIGS. 4, 6 and 8).

The individual data (elements) X0, X1, X2, X3, X4, X5, X6 and X7 of theinput data are sequentially inputted to the shift register 10. Whenthese eight data are held in the shift register 10, they are transmittedfrom the shift register 10 to the hold register 11. Until the eight dataof the next column are held in the shift register 10, the hold register11 holds the eight data transmitted from the shift register 10. As aresult, even if the data are consecutively inputted to the shiftregister 10, the data of one column can be held in the hold register 11.

The data fetching and shifting timings of the shift register 10 and thedata fetching timings of the hold register 11 are controlled by thetiming signals which are generated and outputted by the timing controlunit 22. In the shift register 10, for example, the data are inputtedand shifted at timings of a period T (frequency: φ). The hold register11 receives the data from the shift register 10 at timings of a period8T (frequency: φ/8).

The eight data held in the hold register 11 are sequentially selected bythe multiplexer 12 according to the addresses designated by the addresscounter 23, so that they are transmitted to the multiplier 13. Insynchronism with the inputs of the eight data, the multiplier 13 readsthe DCT transformation coefficients corresponding to the addressesdesignated by the address counter 23 from the coefficient storage ROM14, and performs the multiplication of the DCT transformationcoefficients b, f, d, d, a, c, e and g and the data X2, X6, X0, X4, X1,X3, X5 and X7 sequentially transmitted from the multiplexer 12. Themultiplication results bX2, fX6, dX0, dX4, aX1, cX3, eX5 and gX7 aresequentially transmitted to an adder 15A of the cumulative adder 15. Ofthe DCT transformation coefficients thus read out, the four coefficientsof the first half are the elements of the first to fourth columns of thefirst row of Formula (2), and the four coefficients of the second halfare the elements of the fifth to eighth columns of the fifth row ofFormula (2).

The inputting timings of the data to be inputted from the multiplexer 12to the multiplier 13 is controlled by the timing signal generated by andoutputted from the timing control unit 22, and they are timings(frequency: 4φ) of a quarter of the aforementioned input period T of thedata inputted to the shift register 10 (frequency: 4φ). Moreover, themultiplication results are sequentially transmitted at timings of aquarter of T of (T/4) (frequency: 4φ) from the multiplier 13 to thecumulative adder 15. As a result, the product of the number of themultipliers and the normalized frequency in the first embodiment is[1×4=4].

The cumulative adder 15 comprises of the adder 15A and a register 15Band cumulatively adds the four multiplication results bX2, fX6, dX0 anddX4 of the first half inputted from the multiplier 13. Specifically, thefirst multiplication result bX2 is temporarily held in the register 15B.In synchronism with the next multiplication result fX6 inputted from themultiplier 13, the multiplication result bX2 is transmitted from theregister 15B to the adder 15A, in which the addition of [bX2+fX6] iseffected, and this addition result is temporarily held again in theregister 15B. Like this, for the individual multiplication results dX0and dX4, the multiplication result dX0 is added to the sum [bX2+fX6]temporarily held in the register 15B, and the addition result[bX2+fX6+dX0] is temporarily held in the register 15B. Themultiplication result dX4 is further added to obtain [bX2+fX6+dX0+dX4].This cumulative addition result obtained by adding the fourmultiplication results is transmitted to the demultiplexer 16, so thatit is distributed and inputted to the adder 17 and the subtracter 18.

The four multiplication results aX1, cX3, eX5 and gX7 of the second halfinputted from the multiplier 13 are likewise cumulatively added by thecumulative adder 15. The cumulative addition result [aX1+cX3+eX5+gX7]thus obtained is transmitted to the demultiplexer 16, so that it isdistributed and inputted to the adder 17 and the subtracter 18.

The outputting timings from the cumulative adder 15 to the demultiplexer16 are controlled by the timing signals generated by and outputted fromthe timing control unit 22, and are identical to the input period T(frequency: φ) of the input data.

The adder 17 and the subtracter 18 respectively adds and subtracts thetwo inputted cumulative addition results [bX2+fX6+dX0+dx4] and[aX1+cX3+eX5+gX7]. More specifically, the results of the cumulativeadder 15 are individually inputted in sets of two to the adder 17 andthe subtracter 18, so that the adder 17 determines their sum whereas thesubtracter 18 sequentially determines the differences of the first inputvalues from the next input values, that is, the differences of thevalues inputted n-th (n is an odd number) from the values inputted m-th(m is an even number). Here, as apparent from Formula (2), the double ofthe first cumulative addition result [bX2+fX6+dX0 and dX4] and thedouble of the second cumulative addition result [aX1+cX3+eX5+gX7] areequal to the sum [x0+x7] and the difference [x0-x7], which are theelements of the output data (the inverse DCT operation results),respectively. As a result, the element x0 is obtained from the adder 17,and the element x7 is obtained from the subtracter 18. These twooperation results x0 and x7 are simultaneously stored at the doubleperiod (2T) of the input period T of the input data in the registers 19Aand 19B.

Such operations are also performed for the combinations of the elementsof the first to fourth columns of the second row of the DCTtransformation matrix of Formula (2) and the elements of the fifth toeighth columns of the sixth row, the combinations of the elements of thefirst to fourth columns of the third row and the elements of the fifthto eighth columns of the seventh row, and the combinations of theelements of the first to fourth columns of the fourth row and theelements of the fifth to eighth columns of the eighth row, so that theelements x0, x7, x1, x6, x2, x5, x3 and x4 of the first column of theoutput data are obtained.

As a result, the register 19A holds the elements x0, x1, x2 and x3 ofthe output data outputted from the adder 17. The register 19B holds theelements x7, x6, x5 and x4 of the output data outputted from thesubtracter 18. The eight data (elements) of the first column of the dataare transmitted, when held in the registers 19A and 19B, from theregisters 19A and 19B to the register 20. Until the register 20 holdsthe eight data of the next column, it holds the eight data transmittedfrom the registers 19A and 19B. Here, the transmission timings of thedata from the adder 17 and the subtracter 18 to the registers 19A and19B are controlled by the timing signals generated by and outputted fromthe timing control unit 22, at a period (2T) twice the input period T ofthe input data. Moreover, the data transmissions from the registers 19Aand 19B to the register 20 are performed in a cycle of 8T (frequency:φ/8).

The individual elements x0, x1, x2, x3, x4, x5, x6 and x7 of the outputdata held in the register 20 are sequentially selected by themultiplexer 21 and outputted at timings of the period T (frequency: φ).As a result, for the elements X0, X1, X2, X3, X4, X5, X6 and X7 of thefirst column of the input data inputted for the period T (frequency: φ)to the DCT operation circuit 1, there are sequentially outputted in acycle of T (frequency: φ) the individual elements x0, x1, x2, x3, x4,x5, x6, x6 and x7 of the first column of the one-dimensional (inverse)DCT operation result.

By repeating the aforementioned operations from the second to eighthcolumns of the input data, it is possible to obtain the one-dimensional(inverse) DCT operation results of 8×8.

FIG. 3 is a block diagram schematically showing a DCT operation circuitof a second embodiment according to the invention. In a DCT operationcircuit 2 of this second embodiment, as in the DCT operation circuit 1of the foregoing first embodiment, the data inputted through the shiftregister 10, the hold register 11 and the multiplexer 12, and the DCTtransformation coefficients read out from the coefficient storage ROM 14are multiplied in the multiplier 13. The combination of the input dataand the DCT transformation coefficients to be multiplied is selected bythe address counter 23 which is connected with the multiplexer 12 andthe coefficient storage ROM 14. Moreover, the output data determined byadding the multiplication results by two cumulative adders 30 and 31 areoutputted through the registers 19A, 19B and 20 and the multiplexer 21.Here, in one cumulative adder (a first cumulative adder) 30, themultiplication results sequentially inputted from the adder 13 are addedas they are. In the other cumulative adder (a second cumulative adder)31, the multiplication results sequentially inputted from the adder 13are added after the sign of every other result is inverted by a signinverter 32.

The input/output timings of the data in the individual registers 10, 11,19A, 19B and 20, the multiplexers 12 and 21 and the cumulative adders 30and 31, the sign inverting timings of the sign inverter 32, and theincrement timing of the address counter 23 are controlled according tothe timing signals generated from a timing control unit 22. Here, FIG. 3is a table prepared by using a reference clock CLK (frequency: φ0)inputted to the timing control unit 22; and the frequencies expressed byusing φ (φ is the frequency of the input timings of data to the shiftregister 10) of the timing signals outputted from the timing controlunit 22 to the shift register 10, the hold register 11, the multiplexers12 and 21, the cumulative adders 30 and 31, the sign inverter 32, theregisters 19A, 19B and 20 and the address counter 23.

This DCT operation circuit 2 produces two DCT operation results, whenone column of data of an input matrix are inputted to the multiplier 13,by exploiting the regularity of the DCT transformation coefficientsexpressed by Formula (1).

The DCT operation circuit 2 will be described in detail for the case ofFormula (1), for example, with reference to the timing chart shown inFIG. 4.

The descriptions of the shift register 10, the hold register 11, themultiplexers 12 and 21, the coefficient storage ROM 14, the multiplier13, the registers 19A, 19B and 20, the timing control unit 22 and theaddress counter 23 will be omitted by designating them by the samereference numerals because of the similar construction to the firstembodiment.

The individual data (or elements) X0, X1, X2, x3, X4, X5, X6 and X7 ofthe input data are sequentially inputted at timings of T/4 (frequency:4φ) to the multiplier 13 through the shift register 10, the holdregister 11 and the multiplexer 12. In synchronism with the inputtimings of the data X1, X1, X2, X3, X4, X5, X6 and X7, the DCTtransformation coefficients d, a, b, c, d, e, f and g of the first rowof Formula (1) are sequentially inputted to the multiplier 13 from thecoefficient storage ROM 14.

The individual multiplication results dX0, aX1, bX2, cX3, dX4, eX5, fX6and gX7 obtained by the multiplications in the multiplier 13 aresequentially transmitted at timings of T/4 (frequency: 4φ) to an adder30A of the first cumulative adder 30, and further to an adder 31A of thesecond cumulative adder 31 after the sign of every other result areinverted by the sign inverter 32. By the adders 30A and 31A andregisters 30B and 31B of the individual cumulative adders 30 and 31,moreover, the eight multiplication results are added to obtain[dX0+aX1+bX2+cX3+dX4+eX5+fX6+gX7] from the first cumulative adder 30 and[dX0−aX1+bX2−cX3+dX4−eX5+fX6−gX7] from the second cumulative adder 31.Here, the accumulative additions are similar to those in the cumulativeadder 15 of the foregoing first embodiment excepting that the number ofcumulative additions is seven.

As apparent from Formula (1), the first cumulative adder result[dX0+aX1+bX2+cX3+dX4+eX5+fX6+gX7] and the second cumulative adder result[dX0−aX1+bX2−cX3+dX4−eX5+fX6−gX7] are equal to the elements x0 and x7 ofthe output data (the inverse DCT operation results), respectively. As aresult, the element x0 is obtained from the first cumulative adder 30,and the element x7 is obtained from the second cumulative adder 31.These two operation results x0 and x7 are stored in the registers 19Aand 19B.

By performing such operations for the second to fourth rows (the sevento fifth rows) of the DCT transformation matrix of Formula (1), thereare obtained the elements x0, x1, x2, x3, x4, x5, x6 and x7 of the firstcolumn of the output data. The eight data (elements) of the first columnof the output data are transmitted, when held in the registers 19A and19B, to the register 20, so that they are sequentially selected by andoutputted from the multiplexer 21. As a result, for the elements X0, X1,X2, X3, X4, X5, X6 and X7 of the first column of the input data inputtedfor the period T (frequency: φ) to the DCT operation circuit 1, theelements x0, x1, x2, x3, x4, x5, x6 and x7 of the first column of theone-dimensional inverse DCT operation results are sequentially outputtedin a cycle of the period T (frequency: φ).

By repeating the aforementioned operations for the second to eighthcolumns of the input data, it is possible to obtain the one-dimensionalDCT operation results of 8×8.

Here, the data and the DCT transformation coefficients are inputted tothe multiplier 13 at timings of a quarter (T/4) of the input period T ofthe data (frequency: 4φ) inputted to the shift register 10. Themultiplication results are sequentially transmitted at timings of aquarter (T/4) of the period T (frequency: 4φ) from the multiplier 13 tothe cumulative adders 30 and 31. Therefore, the product of the number ofmultipliers and the normalized frequency in this second embodiment is[1×4=4]. The cumulative addition results are outputted at timings of 2T(frequency: φ/2) from the cumulative adders 30 and 31 to the registers19A and 19B. The timing control unit 22 generates the sign invertingsignals at timings of T/2 (frequency: 2φ) and outputs them to the signinverter 32. As a result, the sign of every other multiplication resultsout of the results inputted in a cycle of T/4 (frequency: 4φ) to thecumulative adder 31 is alternately inverted.

FIG. 5 is a block diagram showing a third embodiment of the DCToperation circuit according to the invention. In a DCT operation circuit3 of this third embodiment, a pair of multiplexers 40 and 41 areconnected with the hold register 11 for holding, for example, eight datainputted through the shift register 10; multipliers 42 and 45 areconnected with the multiplexers 40 and 41, respectively; and coefficientstorage ROMs 43 and 46 are connected with the multipliers 42 and 45,respectively. Although the number is not especially limited, the thirtytwo DCT transformation coefficients (excepting “0”) of Formula (2), forexample, are divided into two groups, so that sixteen coefficients arestored in each of the coefficient storage ROMs 43 and 46.

In the multiplier 42, moreover, the data inputted from the shiftregister 10, the hold register 11 and the multiplexer 40, and the DCTtransformation coefficients read out of the coefficient storage ROM 43are multiplied. In the multiplier 45, the data inputted through the holdregister 11 and the multiplexer 41, and the DCT transformationcoefficients read out of the coefficient storage ROM 46 are multiplied.These operations in the multipliers 42 and 45 are processed in parallel.The combinations, multiplied in the individual multipliers 42 and 45, ofthe input data and the DCT transformation coefficient are selected bythe address counter 23 which is commonly connected with the multiplexers40 and 41 and the coefficient storage ROMs 43 and 46.

An adder 47 is connected with the multipliers 42 and 45, and it adds themultiplication results outputted from the multipliers 42 and 45. Withthe adder 47, there is connected the cumulative adder 15 which furtheradds the two addition results consecutively outputted from the adder 47.

The addition result outputted from the cumulative adder 15 is outputted,as in the DCT operation circuit 1 of the foregoing first embodiment,through the demultiplexer 16 to the adder 17 and the subtracter 18, andthe output data determined by the addition and the subtraction areoutputted through the registers 19A, 19B and 20 and the multiplexer 21.

The input/output timings of the data in the individual registers 10, 11,19A, 19B and 20, the multiplexers 40, 41 and 21 and the cumulative adder15, and the increment timings of the address counter 23 are controlledaccording to the timing signals generated from the timing control unit22. Here, FIG. 5 is a table prepared by using a reference clock CLK(frequency φ0) inputted to the timing control unit 22, and thefrequencies expressed using φ (the frequencies of the input timings ofdata to the shift register 10) of the timing signals outputted from thetiming control unit 22 to the shift register 10, the hold register 11,the multiplexers 40, 41 and 21, the cumulative adder 15, the registers19A, 19B and 20 and the address counter 23.

This DCT operation circuit 3 produces two DCT operation results, whenhalf data of one column in an input matrix are inputted to themultiplier 42 and when the other half data of one column in the inputmatrix are inputted to the multiplier 45, by exploiting the regularityof the DCT transformation coefficients expressed by Formula (2).

The DCT operation circuit 3 will be described in detail for the case ofFormula (2), for example, with reference to the timing chart shown inFIG. 6.

The descriptions of the shift register 10, the hold register 11, thecumulative adder 15, the demultiplexer 16, the adder 17, the subtracter18, the registers 19A, 19B and 20, the multiplexer 21, the timingcontrol unit 22 and the address counter 23 will be omitted bydesignating them by the same reference numerals because of the similarconstruction to the foregoing first embodiment.

Half (four) data X2, X0, X1 and X5 of the eight data inputted throughthe shift register 10 and held in the hold register 11 are sequentiallyselected and transmitted to the multiplier 42 by the multiplexer 40 onthe basis of the addresses designated by the address counter 23. Insynchronism with the individual transfer timings of those data X2, X0,X1 and X5, the other four data X6, X4, X3 and X7 of the hold register 11are sequentially selected and transmitted to the multiplier 45 by themultiplexer 41 on the basis of the address designation of the addresscounter 23.

In synchronism with the inputs of the four data, the multiplier 42sequentially reads out the DCT transformation coefficients correspondingto the addresses designated by the address counter 23, from thecoefficient storage ROM 43, and operates the multiplications of the DCTtransformation coefficients b, d, a and e (of which b and d are the DCTtransformation coefficients of the first and third columns of the firstrow of Formula (2), and a and e are the DCT transformation coefficientsof the fifth and seventh columns of the fifth row of Formula (2)) andthe data X2, X0, X1 and X5 sequentially transmitted from the multiplexer40. In synchronism with the inputs of the four data, the multiplier 45sequentially reads out the DCT transformation coefficients correspondingto the addresses designated by the address counter 23, from thecoefficient storage ROM 46, and operates the multiplications of the DCTtransformation coefficients f, d, c and g (of which f and d are the DCTtransformation coefficients of the second and fourth columns of thefirst row of Formula (2), and c and g are the DCT transformationcoefficients of the sixth and eight columns of the fifth row of Formula(2)) and the data X6, X4, X3 and X7 sequentially transmitted from themultiplexer 41.

The inputting timings of the data inputted from the multiplexers 40 and41 to the multipliers 42 and 45 are controlled by the timing signalsgenerated by and outputted from the timing control unit 22, and they aretimings of one-half (T/2) of the input period T of the data inputted tothe shift register 10 (frequency: 2φ). In short, the operating frequencyof the multipliers 42 and 45 is 2φ. As a result, the product of thenumber of multipliers and the normalized frequency in this thirdembodiment is [2×2=4].

The multiplication results bX2 and fX6, dX0 and dX4, aX1 and cX3, andeX5 and gX7 are in pairs inputted to the adder 47 synchronously from themultiplier 42 and the multiplier 45. Then, the adder 47 performsadditions to output [bX2+fX6], [dX0+dX4], [aX1+cX3) and [eX5+gX7]sequentially to the cumulative adder 15. The input/output timings of thedata of the adder 47 are controlled at timings of T/2 (frequency: 2φ) bythe timing signals generated by and outputted from the timing controlunit 22.

The cumulative adder 15 cumulatively adds the two multiplication results[bX2+fX6] and [dX0+dX4] of the first half inputted from the adder 47.The operation result [bX2+fX6+dX0+dX4] are transmitted to thedemultiplexer 16, and distributed and inputted to the adder 17 and thesubtracter 18. The two multiplication results [aX1+cX3] and [eX5+gX7] ofthe second half inputted from the adder 47 are also added by thecumulative adder 15, so that the operation result [aX1+cX3+eX5+gX7] isfed to the demultiplexer 16, and distributed and inputted to the adder17 and the subtracter 18.

The outputting timings from the cumulative adder 15 to the demultiplexer16 are controlled by the timing signal generated by and outputted fromthe timing control unit 22, and are timings of T/2 (frequency: 2φ).

The two cumulative addition results inputted to the adder 17 and thesubtracter 18, are then processed as in the foregoing first embodimentthrough the adder 17, the subtracter 18 and the registers 19A, 19B and20, and outputted as the output data (the inverse DCT operation results)from the multiplexer 21.

Such operations are also performed for the combinations of the elementsof the first to fourth columns of the second row of the DCTtransformation matrix of Formula (2) and the elements of the fifth toeighth columns of the sixth row, the combinations of the elements of thefirst to fourth columns of the third row and the elements of the fifthto eighth columns of the seventh row, and the combinations of theelements of the first to fourth columns of the fourth row and theelements of the fifth to eighth columns of the eighth row, and theelements x0, x7, x1, x6, x2, x5, x3 and x4 of the first column of theoutput data are obtained.

By repeating the aforementioned operations from the second to eighthcolumns of the input data, it is possible to obtain the one-dimensionalDCT operation results of 8×8.

FIG. 7 is a block diagram showing a fourth embodiment of the DCToperation circuit according to the invention. In a DCT operation circuit4 of this fourth embodiment, a pair of multiplexers 40 and 41 areconnected with the hold register 11 for holding, e.g., eight datainputted through the shift register 10; multipliers 42 and 45 areconnected with the multiplexers 40 and 41, respectively; and coefficientstorage ROMs 43 and 46 are connected with the multipliers 42 and 45,respectively. Although the number is not especially limited, the sixtyfour DCT transformation coefficients of Formula (1), for example, aredivided into two groups, so that thirty two DCT transformationcoefficients are stored in each of the coefficient storage ROMs 43 and46.

In the multiplier 42, moreover, the data inputted from the shiftregister 10, the hold register 11 and the multiplexer 40, and the DCTtransformation coefficients read out of the coefficient storage ROM 43are multiplied. In the multiplier 45, the data inputted through theshift register 10, the hold register 11 and the multiplexer 41, and theDCT transformation coefficients read out of the coefficient storage ROM46 are multiplied. These operations in the multipliers 42 and 45 areprocessed in parallel. The combinations, multiplied in the multipliers42 and 45, of the input data and the DCT transformation coefficient areselected by the address counter 23 which is commonly connected with themultiplexers 40 and 41 and the coefficient storage ROMs 43 and 46.

An adder 47 is connected with the multipliers 42 and 45, and it adds themultiplication results outputted from the multipliers 42 and 45. Thecumulative adder 30 is connected with the adder 47, and the cumulativeadder 31 is connected with the adder 47 through the sign inverter 32.

The four addition results consecutively outputted from the adder 47 areadded as they are in the cumulative adder 30, and added in thecumulative adder 31 after the sign of every other result is inverted bythe sign inverter 32. The output data determined by the two cumulativeadders 30 and 31 are outputted through the registers 19A, 19B and 20 andthe multiplexer 21.

The input/output timings of the data of the registers 10, 11, 19A, 19Band 20, the multiplexers 40, 41 and 21 and the cumulative adders 30 and31, the sign inverting timings of the sign inverter 32, and theincrement timings of the address counter 23 are controlled by the timingsignals generated from the timing control unit 22. Here, FIG. 7 is atable prepared by using a reference clock CLK (frequency φ0) inputted tothe timing control unit 22, and the frequencies expressed using φ (thefrequencies of the input timings of data to the shift register 10) ofthe timing signals outputted from the timing control unit 22 to theshift register 10, the hold register 11, the multiplexers 40, 41 and 21,the cumulative adders 30 and 31, the sign inverter 32, the registers19A, 19B and 20 and the address counter 23.

This DCT operation circuit 4 produces two DCT operation results, whenone-half data of one column in an input matrix are inputted to themultiplier 42 and when the other half data of one column in the inputmatrix are inputted to the multiplier 45, by exploiting the regularityof the DCT transformation coefficients expressed by Formula (1).

The DCT operation circuit 4 will be described in detail for the case ofFormula (1), for example, with reference to a timing chart shown in FIG.8.

The descriptions of the shift register 10, the hold register 11, theregisters 19A, 19B and 20, the multiplexer 21 and the timing controlunit 22 will be omitted by designating them by the same referencenumerals because of the similar construction to the foregoing firstembodiment. Moreover, the descriptions of the cumulative adders 30 and31, the sign inverter 32 and the address counter 23 will be omitted bydesignating them by the same reference numerals because of the similarconstruction to the foregoing second embodiment.

Half (four) data X0, X1, X4 and X5 out of the eight data inputtedthrough the shift register 10 and held in the hold register 11 aresequentially selected and transmitted to the multiplier 42 by themultiplexer 40 on the basis of the addresses designated by the addresscounter 23. In synchronism with the individual transfer timings of thosedata X0, X1, X4 and X5, the other four data X2, X3, X6 and X7 of thehold register 11 are sequentially selected and transmitted to themultiplier 45 by the multiplexer 41 on the basis of the addressdesignation of the address counter 23.

In synchronism with the inputs of the four data, the multiplier 42sequentially reads out the DCT transformation coefficients correspondingto the addresses designated by the address counter 23 from thecoefficient storage ROM 43, and operates the multiplications of the DCTtransformation coefficients d, a, d and e (which are in this order theDCT transformation coefficients of the first, second, fifth and sixthcolumns of the first row of Formula (1)) and the data X0, X1, X4 and X5sequentially transmitted from the multiplexer 40. In synchronism withthe inputs of the four data, the multiplier 45 sequentially reads outthe DCT transformation coefficients corresponding to the addressesdesignated by the address counter 23 from the coefficient storage ROM46, and operates the multiplications of the DCT transformationcoefficients b, c, f and g (which are in this order the DCTtransformation coefficients of the third, fourth, seventh and eighthcolumns of the first row of Formula (1)) and the data X2, X3, X6 and X7sequentially transmitted from the multiplexer 41.

The inputting timings of the data individually inputted from themultiplexers 40 and 41 to the multipliers 42 and 45 are controlled bythe timing signals generated by and outputted from the timing controlunit 22, and are the timings of one-half (T/2) of the input period T ofthe data inputted to the shift register 10 (frequency: 2φ). In short,the operating frequency of the multipliers 42 and 45 is 2φ. As a result,the product of the number of multipliers and the normalized frequency inthis fourth embodiment is [2×2=4].

The multiplication results dX0 and bX2, aX1 and cX3, dX4 and fX6, andeX5 and gX7 are in pairs inputted to the adder 47 synchronously from themultiplier 42 and the multiplier 45. Then, the adder 47 performsadditions to output [dX0+bX2], [aX1+cX3], [dX4+fX6] and [eX5+gX7]sequentially. The input/output of the data of the adder 47 arecontrolled at timings of one-half (T/2) of the input period T of thedata inputted to the shift register 10 (frequency: 2φ) by the timingsignals generated by and outputted from the timing control unit 22.

The addition results outputted from the adder 47 are transmitted to theone cumulative adder 30 and through the sign inverter 32 to the othercumulative adder 31. The cumulative adder 30 cumulatively adds the fouraddition results sequentially transmitted from the adder 47, and outputsthe result [dX0+bX2+aX1+cX3+dX4+fX6+eX5+gX7] to the register 19A. Thesign of every other addition result out of the four addition resultssequentially transmitted from the adder 47 is inverted by the signinverter 32. The cumulative adder 31 cumulatively adds the four additionresults, and outputs the result [dX0+bX2−aX1−cX3+dX4+fX6−eX5−gX7] to theregister 19B.

These two cumulative addition results inputted to the registers 19A and19B are processed as in the foregoing second embodiment and outputted asthe output data (the inverse DCT operation results) from the multiplexer21 through the register 20.

By performing such operations for the second to fourth rows (the sevento fifth rows) of the DCT transformation matrix of Formula (1), thereare obtained the elements x0, x1, x2, x3, x4, x5, x6 and x7 of the firstcolumn of the output data. The eight data (elements) of the first columnof the output data are transmitted, when held in the registers 19A and19B, to the register 20, and they are sequentially selected by andoutputted from the multiplexer 21. As a result, for the elements X0, X1,X2, X3, X4, X5, X6 and X7 of the first column of the input data inputtedin a cycle of T (frequency: φ) to the DCT operation circuit 1, theelements x0, x1, x2, x3, x4, x5, x6 and x7 of the first column of theone-dimensional inverse DCT operation results are sequentially outputtedin a cycle of T (frequency: φ).

By repeating such operations for the second to eighth columns of theinput data, it is possible to obtain the one-dimensional DCT operationresults of 8×8.

Here, the cumulative addition results are outputted at timings of 2T(frequency: φ/2) from the cumulative adders 30 and 31 to the registers19A and 19B. Moreover, the timing control unit 22 generates the signinverting signals at timings of T (frequency: φ) and outputs them to thesign inverter 32. As a result, the sign of every other addition resultout of the addition results inputted in a cycle of T/2 (frequency: 2φ)from the adder 47 to the cumulative adder 31 is inverted.

Here, the DCT operation circuits of the foregoing first, second, thirdand fourth embodiments execute the inverse DCT operations when theseembodiments are applied to an image data decoding process conforming ofthe MPEG or its corresponding standards.

FIG. 9 is a block diagram showing a fifth embodiment of the DCToperation circuit according to the invention. A DCT operation circuit 5of this fifth embodiment executes two-dimensional DCT operations byusing the one-dimensional DCT operation circuit 1, 2, 3 or 4 of theforegoing first, second, third or fourth embodiment. In thistwo-dimensional operation circuit 5, the data of an input matrix areinputted to one one-dimensional DCT operation circuit 1 (2, 3 or 4) toeffect the one-dimensional DCT operations, as described in conjunctionwith the first, second, third or fourth embodiment. This output isinputted to an inverted RAM 6, the output of which is inputted to theother one-dimensional DCT operation circuit 1 (2, 3 or 4). Then, theone-dimensional DCT operations described in conjunction with the first,second, third or fourth embodiment, so that the two-dimensional DCToperation results are obtained.

FIG. 10 is a time chart showing examples of the operation timings of thetwo-dimensional DCT operation circuit of the fifth embodiment. Uponreceiving sixty four input data X00, X01, X02, . . . of an 8×8 matrix,the one-dimensional DCT operation circuit 1 (2, 3 or 4) on the inputside of the two-dimensional DCT operation circuit 5 shown in FIG. 9performs the one-dimensional DCT operations and outputs the operationresults x00, x01, x02, . . . to the inverted RAM 6 after a fixed delayD1. Upon receiving to the sixty four operation results x00, x01, x02, .. . from the one-dimensional DCT operation circuit 1 (2, 3 or 4) on theinput side, the inverted RAM 6 performs the matrix operations forexchanging the column elements and the row elements of the matrixcomprising the received operation results, and outputs the results x00,x10, x20, . . . to the one-dimensional DCT operation circuit 1 (2, 3 or4) on the output side. Upon receiving the sixty four operation resultsx00, x10, x20, . . . from the inverted RAM 6, the one-dimensional DCToperation circuit 1 (2, 3 or 4) on the output side performs anadditional one-dimensional DCT operations for the received operationresults, and outputs the operation results y00, y10, y20, . . . after afixed delay D2. By these operations, it is possible to provide thetwo-dimensional DCT operation results.

When this embodiment is applied to the image data decoding processcomforming to the MPEG or its corresponding standards, for example, eachone-dimensional DCT operation circuit 1 (2, 3 or 4) executes theinverted DCT operations. In this case, the data of the matrix inputtedto the two-dimensional DCT operation circuit 5 of this embodiment arethe data which are prepared, although not specifically shown, byconverting the data of an input image into DCT coefficients by anothercoding two-dimensional DCT operation circuit, quantizing and compressingthe DCT coefficients by a quantizer, and decompressing the compressedcoefficients by a reverse-quantizer. Moreover, the data outputted fromthe two-dimensional DCT operation circuit 5 are transmitted to themotion compensation predicting unit (not shown).

As has been described in detail, the one-dimensional DCT operationcircuit 1 or 2 has either of the two constructions: a construction wherethere is provided one multiplier 13 operated with the normalizedfrequency 4 to multiply the elements of the DCT transformationcoefficients and the elements of the input data sequentially, themultiplication results are added by the cumulative adder 15 to determinea pair of cumulative addition results which correspond to the respectivesums and differences of the paired elements of the data to be outputtedfrom the DCT operation circuit 1, the operations for determining thepaired elements of the output data by adding and subtracting thecumulative addition results by the adder 17 and the subtracter 18specific times the number of which is one-half of the number of elementsof the column of the matrix of the input data, and all the elements ofthe matrix of the output data are determined by performing thoseoperations predetermined times the number of which is equal to thenumber of elements of the row of the matrix of the input data; and aconstruction where the multiplication results obtained by the multiplier13 operating with the normalized frequency 4 are added as they are bythe first cumulative adder 30, and the sign of every other additionresult is inverted to perform the additions by the second cumulativeadder 31 specific times the number of which is one-half of the number ofelements of the row of the matrix of the input data thereby to determinethe elements of the column of the matrix of the output data, and theseoperations are performed specific times the number of which is equal tothe number of elements of the column of the matrix of the input data todetermine all the elements of the matrix of the output data. As aresult, only one multiplier is used to reduce the scale of the DCToperation circuit 1 or 2, and the product of the number of multipliersand the normalized frequency is 4 at most, so that the power consumptioncan be reduced.

The one-dimensional DCT operation circuits 3 or 4 has either of the twoconstructions: a construction where there are provided theone-dimensional DCT operation circuits 3 and 4 which are equipped withthe paired multipliers 42 and 45 to be operated with the normalizedfrequency 2 to effect the multiplications of the elements of one-half ofthe DCT transformation coefficients and the elements of one-half of theinput data sequentially in parallel by the multipliers 42 and 45,thereby to determine the paired cumulative addition resultscorresponding to the respective sums and differences of the pairedelements of the data outputted from the DCT operation circuits, theoperations for determining the paired elements of the output data byadding and subtracting the addition results by the adder 17 and thesubtracter 18, respectively, to determine the elements of the column ofthe matrix of the output data, and the operations are performed specifictimes the number of which is equal to the number of elements of thecolumn of the matrix of the input data to determine all the elements ofthe matrix of the output data; and a construction where themultiplication results obtained from the paired multipliers 42 and 45operated with the normalized frequency 2 are added by the adder 47, theresultant sums are added as they are by the first cumulative adder 30and added by the second cumulative adder 31 after the sign of everyother resultant sum is inverted. These additions are performed forone-half of the number of elements of the column of the matrix of theinput data to determine the elements of the column of the matrix of theoutput data, the operations are performed specific times the number ofwhich is equal to the number of elements of the column of the matrix ofthe input data to determine all the elements of the matrix of the outputdata. As a result, the product of the number of multipliers and thenormalized frequency is 4 at most so that the power consumption can bereduced.

Moreover, the two-dimensional DCT operation circuit 5 is given one ortwo of the aforementioned four constructions including the twoone-dimensional DCT operation circuits 1 (or 2, 3 or 4) and the invertedRAM 6. As a result, the total number of multipliers in the twoone-dimensional DCT operation circuits 1 (or 2, 3 or 4) can be reducedto two or four, thereby reducing the scale of the two-dimensional DCToperation circuit 5. Moreover, the product of the number of multipliersin the two-dimensional DCT operation circuit 5 and the normalizedfrequency is 8 at most, so that the power consumption can be reduced.

Although the invention has been specifically described in conjunctionwith its embodiments, the invention should not be limited to theembodiments but can naturally be modified in various manners withoutdeparting from the gist thereof.

For example, the shift register 10, the hold register 11, themultiplexers 12 and 21, the registers 19A, 19B and 20, the timingcontrol unit 22, the address counter 23 and so on should not be limitedto those of the foregoing embodiments but can be modified in variousmanners.

Moreover, the invention should not be limited to the DCT transformationof 8×8 but can also be applied to a circuit for the DCT transformationsof 4×4 and 16×16.

Our invention has been described mainly on the background which is thefield of is application assumed to be applied to the decoding techniqueby the inverse DCT operations of coded image data. Despite of thisdescription, however, the invention should not be limited to theapplication but can be utilized in a data processing system for the DCTtransformation operations or the inverse DCT transformation operations.

INDUSTRIAL APPLICABILITY

According to the invention, as has been described hereinbefore, only onemultiplier is used in the one-dimensional discrete cosine transformationoperation circuit, so that the scale of the discrete cosinetransformation operation circuit can be reduced, the produce of thenumber of multipliers and the normalized frequency is 4 at most, andhence the power consumption can be reduced.

What is claimed is:
 1. A discrete cosine transformation operationcircuit comprising: an input data holding circuit which holds input datafrom outside in synchronization with a first timing signal having afirst frequency; a coefficient storage unit storing predeterminedtransformation coefficients; a multiplier which multiplies atransformation coefficient from said coefficient storage unit and aninput data from said input data holding circuit in synchronization witha second timing signal having a second frequency which is substantiallyfour times as high as the first frequency; a cumulative adder whichexecutes cumulative adding operations for the multiplication resultssequentially outputted from said multiplier and sequentially providescumulative adding results; and an output circuit which operates insynchronization with a third timing signal having a third frequencylower than the second frequency and which includes operation circuitsexecuting predetermined operations between the cumulative adding resultssequentially outputted from said cumulative adder, to output a discretecosine transformation operation result, wherein the predeterminedtransformation coefficients are DCT transformation coefficients, andwherein the output circuit includes an adder which executes an addingoperation between the cumulative adding results; a subtracter whichexecutes a subtracting operation between the cumulative adding results;a plurality of registers each of which holds one of an output from theadder and an output from the subtracter; and a multiplexer for selectingone of the outputs of said registers, wherein a discrete cosinetransformation operation result is provided from said adder by adding afirst cumulative adding result with a second cumulative adding result inthe cumulative adding results, the other discrete cosine transformationoperation result is provided from said subtracter by subtracting thefirst cumulative adding result with the second cumulative adding, theprovided discrete cosine transformation operation results are stored inthe registers and one of the discrete cosine transformation operationresults held in the registers is outputted from the multiplexer.
 2. Atwo-dimensional discrete cosine transformation operation circuitcomprising: a first operation circuit including a discrete cosinetransformation operation circuit according to claim 1, and executing anoperation of a discrete cosine transformation for data provided from amatrix including a plurality of input data; an inverted RAM receivingdata which are output from said first discrete cosine transformationoperation circuit and which are output so as to form an input matrix,and generating an inverted matrix in which elements of a row andelements of a column of said input matrix are exchanged; and a secondoperation circuit including a discrete cosine transformation operationcircuit according to claim 1, and executing an operation of a discretecosine transformation for data provided from said inverted matrix.
 3. Adiscrete cosine transformation operation circuit according to claim 1,wherein the cumulative adder operates in accordance with the secondfrequency and sequentially provides the cumulative adding results inaccordance with the first frequency.